Axel Jantsch, Royal Institute of Technology, Stockholm, ESDLab

Kalle Tammemäe, Tallinn Technical University, Department of CE

Table of Contents

UMC: A Unifying Multi-paradigm Hardware/Software Codesign Framework for Electronic System Development

UMC: A Unifying Multi-paradigm Hardware/Software Codesign Framework for Electronic System Development

1 Introduction

The Department of Electronics (ELE) at the Royal Institute of Technology in Stockholm (KTH) and the Department of Computer Engineering at the Tallinn Technical University (TTU) has research cooperation and exchange of students since 199?. There is a strong intention and several reasons to intensify this contact: The development and deployment of advanced methods and tools for the design and implementation of electronic products are critical factor for the industry in a very competitive world market. The industry in both Sweden and Estonia relies on local Universities in improving and optimizing their design processes which is a key factor in developing high-quality products in ever shorter development time frames. A study by the consulting firm McKinsey [8] shows, that the most successful companies in the industry have a much smaller than average product development cycle and a much larger than average infrastructure investment per design engineer.

The proposed project addresses this problem area. A successful integration of the traditionally separate design activities of hardware and software development will at the same time increase product quality and decrease product development time. Also, the early design phase of specification development is one of the major bottlenecks in the whole design process. This is due to the unsystematic way of specification development and to the huge affect of a low-quality specification on the entire design process and eventually the product quality. We address this problem by integrating several well established specification languages into the design process. This will also preserve the huge investment in these languages by the industry.

By joining forces of KTH and TTU this project aims at

2 Objectives

Based on KTH's and TTU's earlier work in the areas of hardware/software codesign and hardware synthesis we propose to develop an integrated and unifying framework for specification, HW/SW codesign and synthesis of complex telecommunication systems. The core of our proposition is We want to use several front-end languages for system specification because there exists no single language to day which covers all necessary aspects for the specification of complex telecom systems. In an ongoing international discussion in a series of workshops [1, 2, 3] it is generally agreed that no single existing language is sufficient, and there are two alternatives. Either several languages in the different disciplines of HW and SW development are integrated or a new specification language will be designed. While there is a strong bias of major design tool vendors towards designing a new language, this will be a joint international effort which takes several years. KTH and TTU will take part in this activity but will not compete with it in designing a new language. In the meantime KTH and TTU will join forces to build up a design framework which integrates ongoing activities in both Universities and which allows to efficiently develop methods and tools for system level specification and design for a rapidly growing electronics industry.

Several languages are widely used today in different disciplines: C++ and VHDL are dominant languages for SW and HW design and implementation. SDL [4] is widely used by the telecom industry for specification and design of control dominated concurrent SW. Matlab [5] is a well established language for the modelling and design of complex mathematical algorithms for signal and data processing. Since more than one of the above languages are required for modelling an entire complex electronic system we propose to integrate them in two ways:

The development of an internal representation is at the core of this joint proposal because in order to conduct research and development for methods and tools every research lab has to define and implement an internal representation. This effort can be shared by KTH and TTU and both labs can concentrate better on complementary development of new techniques and tools.

Very often the implementation of an internal representation is the bases for good research but is by itself not an appreciated achievement. However, in this case the integration of several semantically very different languages by means of an internal representation is also an academically challenging task and would be welcomed by industry if successful. We intend to employ a two layer approach which separates semantics from pragmatics as outlined below.

UMC is coordinated with other activities in KTH and TTU to maximise the synergy. Related activities are:

3 Work Packages

We propose four work packages, each of the size of a PhD thesis project. Two of the students will sit permanently in Tallin and two in Stockholm with regular exchanges and common meetings.

The four work packages are:

3.1 Work Package 1: IRSYD

The development of a common internal representation is an ideal project for collaboration because all parties benefit heavily. The necessary development and implementation effort can be shared among the collaborators and all developed techniques and tools can be used by all partners as a basis for further work. Thus, the partners benefit in two ways: the costs are shared and therefore lower for individual parties and the results are also shared and therefore higher than if each group would work alone.

The development of IRSYD, an Internal Representation for System Description, has been started at KTH in the beginning of 1997 and has resulted in a report [6] and a presentation at the Second Workshop on System Design Languages [7]. However, this has emerged from the internal representation for hardware synthesis in an ad-hoc manner. During this work it has been realized clearly that there is a fundamental problem that has to be treated thoroughly. An internal representation that supports several conceptually different front-end languages can be defined in two different ways:

  1. It can be based on low level semantic concepts which are powerful enough to represent all semantic concepts of the front-end languages. For instance all communication between concurrent processes could be modelled in terms of shared variables and all communication primitives of the front-end languages such as message passing and blocking and buffered communication would be compiled into a shared memory based representation. The advantage is that a fairly small set of semantic primitives would suffice to support several front-end languages. The disadvantage is that information would be lost during the compilation process. After compilation the original concept of the front-end language could not be reconstructed. For instance if in the front-end language description it is apparent that a communication channel is only used by two processes this information might be lost after compilation. Thus, analysis and synthesis tools cannot safely assume that only two processes are using the channel and will be forced to dimension the capacity and functionality of the channel for the worst case.
  2. The other alternative is to represent every important semantic concept from all front-end languages directly in the internal representation. This approach avoids any loss of information but fails to truly integrate the front-end languages and for each new language new concepts must be added and synthesis and analysis tools must be adapted. This would in effect reduce one of the main benefits of a common internal representation, i.e. the reuse of techniques and tools for different front-end languages.
In UMC we propose a two layer approach which avoids the disadvantages of both alternatives. The internal representation consists of two layers: the lower layer constitutes the semantic level and the upper layer the pragmatic level. At the semantic layer IRSYD will provide all semantic concepts that are necessary to represent the proposed front-end languages. The concepts can be fairly primitive but can also be complex and powerful if desirable. No matter how directly these modelling concepts represent front-end language concepts, no information will be lost due to the second layer, which captures the pragmatics of the front-end languages. The challenges are to define the semantic layer and to make the pragmatic layer consistent and sufficiently formal.

In addition IRSYD will have a means to represent non-functional information. This allows tools communicate with each other through IRSYD, for instance to document design decisions and store analysis results.

The result of this workpackage will be a definition of IRSYD, an implementation of IRSYD in terms of C++ classes, and the definition and implementation of a mapping from Matlab onto IRSYD.

3.2 Work Package 2: Cosimulation

Traditionally cosimulation has to been the main methodology for design validation. Notwithstanding recent progress in formal verification techniques, they are not applicable to large and complex heterogeneous systems, but only to refined descriptions of a single unit or function. Therefore, the simulation remains the main methodology for validation at the system level. Simulation performance depends heavily on the abstraction level of the system model. Thus, it is beneficial to simulate components modelled at different abstraction levels together to be able to concentrate only on some parts of the system while modelling other parts at a high functional level. This means, that simulation has to be done at different design representation levels (event-based, cycle-based, reason-based).

Simulation has to be transparent over different design refinement stages starting from generated IRSYD until synthesized design, partitioned into units in different implementation domains (HW, SW).

Consequently, the cosimulation subsystem of UMC has to implement following functions:

  1. IRSYD graph animation,
  2. IRSYD graph animation together with foreign simulation packages for refined system components, after the HW or SW code generation.
  3. Cosimulation between HW and SW domains, running on foreign simulators/interpreters supplied with communication interfaces. The basic idea is to keep up enough synchronization points to follow simulation at higher level.
IRSYD graph animation can be performed based on interactive graph browsers, but cosimulation between different domains has to be organized using specific communication drivers from a work package database or library.

Simulation experiences obtained during elaborating HW/SW co-design package AKKA [9], can be fully exploited for building up an IRSYD centric cosimulation environment.

3.3 Work Package 3: Partitioning

Partitioning is the task of clustering objects into groups such, that a given objective function is optimised with respect to a set of design constraints [10]

Partitioning is main tool of divide and conquer design methodology for solving large problems. Several partitioning algorithms, for instance simulated annealing, tabu search, knapsack stuffing [11], hierarchical clustering, etc. can be applied. In case of UMC, partitioning methods should be revised due to two-layer representation of information usable during partitioning. The basic idea is to compare different partitioning methods by arranging competition between them and to select the best one for our problem.

Partitioning is one of the most fragile parts of codesign because its result defines the final structure for implementation. Very often this task is left to designer or done semi-automatically. Hence, partitioning is also a problem of human-computer interaction. Due to the enormous amount of information collected for partitioning during the construction of the IRSYD representation and generated by analysis and estimation tools, there is a demand for fast front-end classification method to aid the designer to obtain and assess the data. We propose to investigate fast and low complexity bulk data sorting methods to obtain a monotonous function over system properties [12].

In addition, the following sub-problems have to be solved:

  1. Representation and visualization of the problem before, during, and after partitioning;
  2. Interactive retrieval and visualization of information about system components and clusters of components;
  3. Interactive system partitioning guided by the designer's experience;
  4. Implementing backtracking for documentation and re-partitioning.

3.4 Work Package 4: Estimation

In order to link early design phases with implementation issues, some important properties must be estimated long before an implementation is available for analysis. The estimation algorithms will operate on IRSYD and add the estimation results to the IRSYD description. The properties to be estimated are performance, cost and power. The following aspects are important and will be emphasized:

The result of this work package will be the development of estimation algorithms for performance, cost, and power consumption, their implementation based on IRSYD, and the visualization of their results.

4 References

[1]
SLD'96 System Level Design Workshop, October 1st - 2nd, 1996, Dallas, Texas, http://www.cfi.org/sld/
[2]
First Workshop on Systems Design Languages, April 7th - 8th, 1997, San Jose, California, http://www.cfi.org/sld/sldl/
[3]
Second Workshop on System Level Design Language, July 8th - 10th, 1997, Il Chiocco, Italy, http://www.ecsi.org/ecsi/sld.html
[4]
A. Olsen, O Färgemand, B. Møller-Pedersen, R. Reed, and J.R.W. Smith, Systems Engineering with SDL-92, North Holland, 1995.
[5]
MATLAB: High-performance Numeric Computation and Visualization Software. User's Guide, 1992.
[6]
Peeter Ellervee, Shashi Kumar, Axel Jantsch, Ahmed Hemani, Bengt Svantesson, Johnny Öberg, and Ingo Sander, IRSYD - An Internal Representation for System Description. Version 0.1, Electronic System Design Laboratory, Department of Electronics, Royal Institute of Technology, report no. TRITA-ESD-1997-10, ESDlab, KTH-Electrum, Electrum 229, S-16440 Kista, Sweden, 1997.
[7]
Shashi Kumar, Axel Jantsch, Peeter Ellervee, Ahmed Hemani, and Anshul Kumar, "Internal Representation for Specification and Design of Heterogeneous Systems", Second Workshop on Systems Design Languages, Italy, July 1997.
[8]
J. Kluge, L. Stein, E. Krubasik, I. Beyer, D. Düsedau, and W. Huhn, Wachstum durch Verzicht: Schneller Wandel zur Weltklasse - Vorbild Elektronikindustrie, McKinsey and Company, Inc., Schäfer und Pöschel Verlag, 1994.
[9]
Kalle Tammemäe, Mattias O'Nils, Axel Jantsch, and Ahmed Hemani, "AKKA: A Tool-Kit for Cosynthesis and Prototyping", IEE Digest No.96/036 of Colloquium on Hardware-software Cosynthesis for Reconfigurable Systems, pp. 8/1-8/8, Bristol, February 22, 1996.
[10]
D.D. Gajski, High-level synthesis: introduction to chip and system design, Kluwer Academic Publisher, 1992.
[11]
M. O'Nils, Hardware/Software Partitioning of Embedded Computer Systems, Licentium Thesis, KTH, 1996.
[12]
Leo Vyhandu "Fast methods for Data Analysis and Processing", Transactions of the Tallinn Technical University, 1986.